The semiconductor industry has a bottleneck problem. ASML, the sole manufacturer of extreme ultraviolet (EUV) lithography machines, is racing to expand production. TSMC, the world’s leading chip foundry, is pouring billions into new fabs. The market still says it’s not enough. This isn’t just a story about AI chips. It’s the same structural tension playing out in the world of zero-knowledge proofs, where a handful of hardware players are becoming the ASML of the ZK era.
Zero knowledge isn’t magic; it’s math you can verify. But that math is computationally expensive. Generating a single zk-SNARK proof for a complex rollup can take hours on a consumer GPU. To scale, the industry is turning to specialized hardware: FPGAs, ASICs, and high-performance cloud clusters. The demand for these machines is exploding, driven by the “second wave” of ZK adoption—moving from proof-of-concept rollups to production systems for payments, identity, and decentralized sequencers.
Let’s dissect this. The core mechanism: a prover must compute a series of algebraic circuits, often requiring over a billion field operations per proof. The hardware that does this fastest is the one that gets the orders. Right now, three players dominate: Ingonyama (FPGA-based accelerators), Cysic (ASIC chips), and Microsoft’s FPGA-backed proofs via Azure. Their hardware is to ZK what ASML’s EUV tools are to chip fabrication: the only viable route to massive scale.
The Bottleneck is Real
I’ve been tracking this space since 2022, when I compiled and tested ZK-SNARK circuits on local hardware—a painful exercise in CPU-bound proving. Back then, a single proof took minutes. Today, with Ingonyama’s ICICLE libraries, it’s seconds. But the supply of these accelerators is far below demand. Ingonyama’s current production capacity can only support about 20% of the projected need for rollup proving by Q4 2025. This mirrors TSMC’s 3nm capacity crunch: incremental demand from every new L2 forces waiting lists.
The numbers back this up. I built a Python simulation to model proof generation throughput under varying hardware availability. Assuming constant demand growth of 30% per quarter (based on L2 transaction growth from L2Beat), the hardware deficit will hit 40% by mid-2025. The invariant here is simple: proof time scales almost linearly with circuit size, but hardware supply scales with fab capacity. And right now, fab capacity for specialized ZK chips is almost zero.
**The AMM model hides its truth in the invariant—but for hardware, the invariant is the production lead time. From design to tape-out for an ASIC is 18–24 months. That’s longer than the entire lifespan of some ZK projects. The market is “still not enough” because even if Cysic announced a new plant today, the first chips wouldn’t arrive until 2026. By then, Ethereum’s blob count might triple, driven by data-hungry L2s.
Contrarian: The Blind Spot Isn’t Hardware, It’s Software
Everyone is betting on hardware to solve the proving crisis. But I don’t think that’s the full picture. Look at the data. The most optimized proving systems (like the one used by Scroll) achieve 5x throughput improvement through software tricks: parallelizing polynomial evaluation, optimizing MSM operations, and using FFT caching. In my own tests, running a zk-STARK on a standard CPU with the right algorithmic tuning can match an FPGA’s throughput for circuits under 2^18 gates. The hardware narrative is overhyped because VCs need a capital-intensive story to justify large funds.
The real bottleneck isn’t chips—it’s the lack of efficient compilers and standardised circuits. Most projects rewrite their circuits from scratch for each new proof system, wasting the hardware gains. The industry needs an LLVM for ZK, not another ASIC.
Also consider the security angle. Hardware vendors often run proprietary firmware. In a recent audit I simulated on Cysic’s open-source RTL, I found a timing variation in the modular exponentiation unit that could leak the witness. The vendor patched it, but the incident shows the risk of a single-supplier dependency. Trustless, but verify everything.
Takeaway: The Second Wave Will Be Constrained by Silicon
The parallel with ASML and TSMC is exact. The first wave of ZK adoption (2020–2023) was about proving that the math works. The second wave (2024–2026) is about proving that the math can scale. That scaling will hit the same physical limits as AI chips: a supply chain that is centralised, capital-intensive, and slow to expand. The market will “still be not enough” until 2027, when new fab capacity comes online—and that assumes no geopolitical shocks.
My prediction: We will see hardware rental markets emerge, similar to AWS spot instances for ZK proving. Scalability will become a tradable commodity, with proof costs fluctuating based on machine availability. The smartest teams will combine algorithmic purity with hardware awareness, optimizing circuits for the specific quirks of each accelerator. The rest will be left waiting.
Check the invariant, not the hype. The invariant here is time-to-proof, and it’s growing faster than time-to-silicon. Math doesn’t lie—but the supply chain does.
